In recent years, a demand for liquid crystal display devices for use in large-screen liquid crystal TV sets as well as for use in portable telephones (such as mobile phones or cellular phones), notebook PCs, and monitors has expanded. As these liquid crystal display devices, the liquid crystal display devices with an active matrix driving system that enables high-resolution display are utilized. First, a typical configuration of the liquid crystal display device with the active matrix driving system will be outlined with reference to FIG. 14. In FIG. 14, a main configuration connected to one pixel in a liquid crystal display unit is schematically shown in the form of an equivalent circuit.
Referring to FIG. 14, a display unit 960 of the liquid crystal display device with the active matrix driving system generally comprises a semiconductor substrate, an opposed substrate, and a structure with liquid crystals sealed therein between these opposed two substrates. In the semiconductor substrate, transparent pixel electrodes 964 and thin-film transistors (TFTs) 963 (in the case of a color SXGA panel, for example, 1280×3 pixel rows×1024 pixel columns) are arranged in a matrix form. On the entire surface of the opposed substrate, one transparent electrode 967 is formed.
Turning on/off of a TFT 963 having a switching function is controlled by a scan signal. When the TFT 963 is turned on, a gray scale signal voltage corresponding to a video data signal is applied to a pixel electrode 964. The transmissivity of a liquid crystal changes due to a difference in potential between each of the pixel electrodes 964 and the opposed substrate electrode 967. Even after the TFT 963 has been turned off, the difference in potential is held at a liquid crystal capacitance 965 and an auxiliary capacitance 966 for a certain time interval, thereby displaying an image.
On the semiconductor substrate, data lines 962 that send a plurality of levels of voltage (gray scale voltages) applied to the respective pixel electrodes 964 and scan lines 961 that send scan signals are arranged in a matrix form (in the case of the color SXGA panel, 1280×3 data lines and 1024 scan lines are arranged). The scan lines 961 and the data lines 962 become large capacitive loads due to capacitances generated at mutual intersections and liquid crystal capacitances sandwiched with the opposed substrate electrode.
The scan signal is supplied to a scan line 961 by a gate driver 970, and supply of the gray scale signal voltage to each of the pixel electrodes 964 is performed from a data driver 980 through a data line 962. The gate driver 970 and the data driver 980 are controlled by a display controller 950. A clock CLK, a control signal, and the like are supplied to each of the gate driver 970 and the data driver 980 from the display controller 950. Supply voltages are supplied to each of the gate driver 970 and the data driver 980 from a voltage circuit 940. Video data is supplied to the data driver 980. Currently, digital data has become wide-spread use, as the video data.
Rewriting of data for one screen is performed in one frame time interval (usually, approximately 0.017 seconds at a time of 60 Hz driving), and each pixel row (each line) is selected one by one for each scan line. The gray scale voltage signal is supplied from each data line within the time interval of the selection. There cased in which a plurality of pixel rows may be simultaneously selected, or driving may be performed at a frame frequency of 60 Hz or higher.
While the gate driver 970 should supply at least a binary scan signal, the data driver 980 needs to drive the data line by the gray scale voltage signal of multi-valued levels corresponding to the number of gray scales. For this reason, the data driver 980 includes a digital-to-analog converter circuit (DAC) constituted from a decoder that converts the video data to an analog voltage and an operational amplifier that amplifies the analog voltage and outputs the amplified analog voltage to a corresponding data line 962.
As a method of driving large-screen display devices such as the monitor and the liquid crystal TV sets, a dot inversion driving scheme capable of realizing high picture quality is adopted. In the dot inversion driving scheme, an opposed substrate electrode voltage VCOM is set to a constant voltage and voltage polarities held in adjacent pixels are mutually opposite in the display panel 960 in FIG. 14. For this reason, the polarities of the voltages output to the adjacent data lines 962 become positive-polarity and negative-polarity with respect to the opposed substrate electrode voltage VCOM. In the dot inversion driving, polarity inversion of a data line is usually performed for each horizontal period. When a data line load capacitance is especially large, or when a frame frequency is high, a driving method in which the polarity inversion is performed for each N horizontal periods (in which N is an integer not less than two) is also employed.
FIG. 15A is a diagram showing a configuration of an output amplifier circuit (output circuit) in a data driver that drives a data line (refer to Patent Document 1 or the like). FIG. 15B is a timing diagram for explaining an operation in FIG. 15A.
The output amplifier circuit includes a differential stage 900 with a non-inverting input terminal thereof connected to an input terminal N1, a pMOS transistor M93 having a source thereof connected to a first power supply terminal (VDD), a gate thereof connected to a first output of the differential stage 900, and a drain thereof connected to an output terminal N3, and an nMOS transistor M94 having a source thereof connected to a second power supply terminal (VSS), a gate thereof connected to a second output of the differential stage 900, and a drain thereof connected to the output terminal N3. The output terminal N3 is connected to an inverting input terminal of the differential stage 900. An output switch SW90 is provided between the output terminal N3 of the output amplifier circuit and a load (data line) 90.
The output switch SW90 is controlled to be in an off state for a predetermined time interval (T1) from a start of each data period (t1H) in order to prevent degradation of display. The degradation of display is caused by transition noise at a time of change of an input signal (analog data) which is supplied to the input terminal N1. This noise is amplified at the output amplifier circuit, and is then transmitted to the load (data line) 90, thereby causing the degradation of display. In the time interval (T1) where a signal HSTB in FIG. 15B is High, transition of an analog data signal is completed. In a time interval (T2) where the signal HSTB is Low (T2), the output switch SW90 is turned on. The load (data line) 90 is thereby driven by a gray scale voltage that has been output from the output amplifier circuit, corresponding to the input signal.
When a large-sized high-resolution LCD panel is driven, the capacitance of the load 90 is increased, and one data period (t1H) is shortened. For this reason, due to an on resistance of the output switch SW90, a driving speed becomes insufficient. Further, since charging and discharging are performed through the output switch SW90, power dissipation and heat generation are also increased due to the on resistance of the output switch SW90.
In order to reduce the resistance of the output switch SW90 to cope with this problem, the size of the output switch SW90 needs to be increased. An increase in the area of the output amplifier circuit is thereby brought about.
A related art of an amplifier in which there is omitted an output switch will be described below. FIG. 16 is a diagram showing a configuration of a drive circuit disclosed in Patent Document 2, in which the output switch between the amplifier and a data line is eliminated. Referring to FIG. 16, this drive circuit 201 includes differential units 202 and 203, switching units 204 and 205, output units 206, 207, 208, and 209, and display output terminals 210 and 211 of the amplifier, and a control circuit 212 that controls these circuits. Gray scale voltages corresponding to display data are supplied to first inputs of the differential units 202 and 203, respectively. The switching unit 204 selectively connects an output of the differential unit 202 to one of the output units 206 and 208. The switching unit 205 selectively connects an output of the differential unit 203 to one of the output units 207 and 209. The switching unit 204 further connects one of the display output terminals 210 and 211 to a second input of the display unit 202. Likewise, the switching unit 205 connects one of the display output terminals 210 and 211 to a second input of the differential unit 203. The four output units 206, 207, 208, and 209 are provided for the display output terminals 210 and 211. Each of the output units 206 and 208 outputs a positive-polarity signal, while each of the output units 207 and 209 outputs a negative-polarity signal. Each of the output units 206 and 208 is configured to have high charging capability, and each of the output units 207 and 209 is configured to have high discharging capability. Signals such as a clock signal CLK, a latch signal STB, a polarity signal POL are supplied to the control circuit 212. The control circuit 212 generates a control signal necessary for controlling each unit. The control circuit 212 includes a bias voltage generation unit 213 that supplies a bias voltage to a constant current source in each of the differential unit and the output unit.
To the display output terminal 210, the output unit 206 that outputs the positive-polarity signal and the output unit 209 that outputs the negative-polarity signal are connected. The control circuit 212 controls the output units 206 and 209 so that only one of the output units 206 and 209 is activated. To the display output terminal 211, the output unit 207 that outputs the negative-polarity signal and the output unit 208 that outputs the positive-polarity signal are connected. The control circuit 212 controls the output units 207 and 208 so that only one of the output units 207 and 208 is activated. The signals of the polarities that are different to each other are generated for the display output terminals 210 and 211, in order to implement dot inversion driving. In a certain horizontal period, the output unit 206 outputs the positive-polarity signal to the display output terminal 210, and the output unit 207 outputs the negative-polarity signal to the display output terminal 211. In this case, the output units 208 and 209 are deactivated. On the other hand, in the next horizontal period, the output unit 208 outputs the positive-polarity signal to the display output terminal 211, and the output unit 209 outputs the negative-polarity signal to the display output terminal 210. In this case, the output units 206 and 207 are deactivated. There is no need for providing the output switch between each of the output terminals 210 and 211 and each of the output units 206, 207, 208, and 209.
FIGS. 17A and 17B are diagrams respectively showing a detailed configuration and operation of the drive circuit in FIG. 16 (refer to Patent Document 2). The differential unit 202 in FIG. 16 is composed of transistors 21 to 24 and a current source 25, and the differential unit 203 in FIG. 16 is composed of transistors 31 to 34 and a current source 35. Each of the differential units 202 and 203 in FIG. 16 is composed of medium-voltage elements. The switching unit 204 in FIG. 16 is composed of switches 41 to 46, and the switching unit 205 in FIG. 16 is composed of switches 51 to 56. The switches 45, 46, 55, and 56 that constitute the switching units 204 and 205 in FIG. 16 are composed of high-voltage elements, and the other switches except these switches are composed of medium-voltage elements. The output unit 206 in FIG. 16 is composed of transistors 61 and 62, while the output unit 207 is composed of transistors 71 and 72. The output unit 208 is composed of transistors 81 and 82, while the output unit 209 is composed of transistors 91 and 92. Each of the output units 206, 207, 208, and 209 is composed of high-voltage elements.
Patent Document 3 discloses a configuration as shown in FIG. 18, as an offset cancelling amplifier, though an object and control of the offset cancelling amplifier in Patent Document 3 are different from those of the present invention. Referring to FIG. 18, a differential circuit 10 includes nMOS transistors M3 and M4 having sources thereof connected in common to form a differential pair, an nMOS transistor M9 (current source) connected to the common source of the nMOS transistors M3 and M4, and a current mirror circuit formed of pMOS transistors M1 and M2 with drains thereof respectively connected to drains of the nMOS transistors M3 and M4. The offset cancelling amplifier includes a pMOS transistor M7 having a source thereof connected to a power supply terminal VDD and a gate thereof connected to a drain of the nMOS transistor M4. A drain N1 of the pMOS transistor M7 is fed back to a gate of the transistor M3 through a switch SW2. The offset cancelling amplifier includes an nMOS transistor M10 (current source transistor for pulling down) having a source thereof connected to the ground, a drain thereof connected to the drain N1 of the pMOS transistor M7. A gate of the nMOS transistor M10 receives a bias voltage VBB. The offset cancelling amplifier includes a pMOS transistor M11 having a source thereof connected to the power supply terminal VDD and a drain thereof connected to an output terminal OUT, an nMOS transistor M12 having a source thereof connected to a power supply terminal VSS and a drain thereof connected to the output terminal OUT, a pMOS transistor M13 that is connected between the gate of the transistor M7 and a gate of the transistor M11 and has a gate thereof connected to a control signal CON, a nMOS transistor M15 that is connected between a gate of the transistor M12 and the gate of the transistor M10 and has a gate thereof connected to an inverted signal of the control signal CON (output of an inverter INV2), a pMOS transistor M14 having a source thereof connected to the power supply terminal VDD and a drain thereof connected to the gate of the transistor M11, and an nMOS transistor M16 having a source thereof connected to the power supply terminal VSS and a drain thereof connected to the gate of the transistor M12. A gate of the pMOS transistor M14 receives a signal obtained by inverting the control signal CON by an inverter INV1. The nMOS transistor 16 receives a signal obtained by inverting the control signal CON by the inverter INV2 and then further inverting the resulting signal by an inverter INV3.
An offset cancel circuit 11 that stores an offset state is connected to the input stage differential pair of the transistors M3 and M4. The offset cancel circuit 11 stores a voltage (IN+Vof) obtained by adding an offset voltage Vof to an input voltage IN.
The offset cancel circuit 11 includes offset cancelling (nMOS) transistors M5 and M6 arranged in parallel with the differential pair transistors M3 and M4, an (nMOS) current source transistor M8 connected to a commonly-connected source of the transistors M5 and M6, and an offset cancel capacitance C1 connected to a gate of the transistor M5. A predetermined bias voltage VBB is applied to respective gates of the current source transistors M8 and M9 and the gate of the current source transistor M10.
In an offset cancel time interval, a switch SW2 is turned off, and switches SW1 and SW3 are turned on, thereby applying an input voltage IN to gates of the transistors M3, M4, and M6. In this case, the drain N1 of the transistor M7 is fed back to a gate N2 of the transistor M5 in the offset cancel circuit 11 through the switch SW3, thereby forming a voltage follower configuration for the input voltage IN. As a result, the voltage (IN+Vof) obtained by adding the offset voltage Vof to the input voltage IN is stored in the capacitance C1.
In the subsequent operational amplifier operation time interval, the switch SW2 is turned on, and the switches SW1 and SW3 are turned off, thereby causing the drain N1 of the output transistor M7 to be fed back to a gate of the transistor M3. The voltage at the gate of each of the transistors M5 and M6 of the offset cancel circuit 11 is maintained. As a result, the gate of the transistor M3 is stablized at the input voltage IN, and the input voltage IN is generated at the drain N1 of the transistor M7.
Further, the (pMOS) transistor M11 and the (nMOS) transistor M12 (in a second output stage) are connected in parallel with the transistors M7 and M10 (in a first output stage), and the switching transistor M13 and M14 (both of which are pMOS transistors) are provided for a gate of the transistor M11. Further, the switching transistors M15 and M16 (both of which are nMOS transistors) are connected to the gate of the transistor M12, which is a second output current source transistor. These switching transistors M12, M14, M15, and M16 are respectively controlled to be turned on or off responsive to the control signal CON, the inverted control signal of the control signal CON that is inverted by the inverter INV1, the inverted control signal of the control signal CON that is inverted by the inverter INV2, and the inverted control signal obtained by inverting the control signal CON by the inverters INV2 and INV3.
In this operational amplifier circuit, when the offset cancel time interval is completed, the transistors M11 and M12 are disconnected from the transistors M7 and M10, and the gates of the transistors M11 and M12 are respectively connected to a power supply VDD and the ground GND, thereby causing the transistors M11 and M12 not to be operated. That is, by switching the control signal CON from a Low level to a High level, the transistors M13 and M15 are both turned off, and the transistors M14 and M16 are both turned on. Then, a switch SW4 is turned on, so that the operational amplifier circuit enters into the operation time interval. As a result, in the subsequent operational amplifier operation time interval, a control operation on the transistor M11 using an output of the differential circuit 10 is stopped, so that the transistor M11 is deactivated. Likewise, the output current source transistor M12 is also deactivated.
FIG. 18B is a table showing operations of the output unit of the circuit in FIG. 18A. In the offset cancel time interval, the switch SW4 is turned off, the transistors M13 and M15 are turned on, and the transistors M14 and M16 are turned off. Then, the second output stage (M11, M12) is activated. In the operational amplifier operation time interval, the switch SW4 is turned on, the transistors M13 and M15 are turned off, and the transistors M14 and M16 are turned on. Then, the second output stage (M11, M12) is deactivated.
[Patent Document 1]
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